This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .

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BCC includes a small run-time with interrupt support and Pthreads library. This allows lwon3 users to quickly define a suitable custom configuration. The LEON4 processor has the following features: It is highly configurable, and was designed for embedded applications with the following features on-chip:.

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Views Read Edit View history. Aeroflex Gaisler – Device: SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems.

For industrial and high-rel applications, ports for VxWorks 5. Pre-synthesized FPGA programming files are also provided.

It is thus possible to instantiate several processor cores in the same design with different configurations. Retrieved from ” http: By using this site, you agree to the Terms of Use and Privacy Policy. The Porcessor has the following on-chip functions: This article relies too much on references to primary sources.

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LEON3 32-bit processor core

It is described in synthesizable VHDL. It features the following:.

It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset Keon3 errors in all on-chip RAM memories. This article is about the family of microprocessors. More information regarding these models can is available on the Aeroflex Gaisler website. The goals have keon3 to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient SET errors in combinational logic.

Your rating has been changed, thanks for processsor While the LEON2 -FT design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.

LEON3 Processor | eASIC Corporation

LEON has a dual license model: Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1. Hardware iCE Stratix Virtex. It is highly configurable, and was designed for embedded applications with the following features on-chip: The model is highly configurable, and particularly pocessor for system-on-a-chip SoC designs.


Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. November Learn how and when to remove this template message. Archived from the original PDF on The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.

It is possible to perform source-level symbolic debugging, either on a simulator or using real proceseor hardware. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications. The NGMP has the following on-chip functions:.

LEON3 Processor – MechatronicsUSP

Please improve this by adding secondary or tertiary sources. This website requires javascript to function properly. Another objective was to be able to manufacture in a Single event upset SEU tolerant sensitive semiconductor process.